| Title | Date | Abstract | From |
| Metallurgy, Surface Prep. and Bonding for Cryogenic and Superconducting Hybrid Applications | Quantum Sci. Technol.3 (2018) | This Paper by the Quantum Computing groups at Google and UCSB describes the materials and processes (including SET hybrid bonders and Ontos Atmospheric Plasma) which are now routinely used to produce leading-edge quantum computing components operating at superconducting temperatures. | SET Manuscript |
| Flip-chip assembly for focal plane array | IST:GST, India, Nov.2017 | Considerations, constraints and processes for reliable assembly of FPA | SET Presentation |
| Toward a flip-chip bonder dedicated to direct bonding for production environment | IWLPC, USA Oct. 2017 | 3D vertical integration of components is now an industrial reality. Considerations and results on direct bonding for HVM precise assembly are presented. | SET Manuscript Presentation |
| Flip-chip bonding: how to meet the high accuracy requirements ? | EMPC, Poland, Sep.2017 | Flip-chip bonding: how to meet the high accuracy requirements ? | SET Presentation |
| High Accuracy Flip-Chip Equipement | SEMI – 3D-Summit, Jan. 2016 This material is posted here with permission of SEMI. |
Consideration on the design of high precision Flip-chip bonder for mass production | SET Presentation |
| Results of the 2015 testbeam of 180 nm AMS High-Voltage CMOS sensor prototype | June 30, 2016 | Active pixel sensors based on the High-Voltage CMOS technology are being investigated as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC | DPNC, University of Geneva, CH Manuscript |
| Evaluation of Sn-based Microbumping Technology for Hybrid IR Detectors, 10µm Pitch to 5µm Pitch | ECTC 2015 This material is posted here with permission of IEEE. |
Hybridization of Infrared detectors has relied on Indium balling for the last decades. Whereas this well-established process has proven its reliability through out the years, it becomes challenging to further decrease the balling pitch below 10µm, due to balling volume limitation. | IMEC, BE – Sofradir, FR |
| Challenges to be faced on Flip-chip Bonder to achieve Precision Requirements in Different Environments | MINAPAD 2015 This material is posted here with permission of IMAPS. |
This paper explores some challenges faced by flip-chip bonders, depending on the applications to be achieved and the environment, Research and Development or Production. | SET |
| Interconnect and bonding techniques for pixelated X-ray and gamma-ray detectors | 10th International Conference on Position Sensitive Detectors (2014) | In the last decade, the Detector Development at the Technology departmentof the Science and Technology Facilities Council (STFC), U.K., established a variety of fabrication and bonding techniques to build pixelated X-ray and y-ray detector systems such as the spectroscopic X-ray imaging detector HEXITEC. | UNIVERSITY OF SURREY, Guilford, Surrey, U.K. |
| Microbumping Technology for Hybrid IR detectors, 10µm pitch and beyond | EPTC 2014 Singapore |
In order to assess the feasability of a more mass-manufacturable process, IMEC has developed microbump technologies down to 10 µm pitch. The microbumps are based on Cu/Ni/Sn semi additive plating and built at wafer level using a process fully compatible with standard packaging infrastructures | IMEC Leuven, Belgium SOFRADIR Veurey-Voroize, France |
| Development done on Device Bonder to address 3D requirements in a production environment | IWLPC2014 San Jose, CA |
This paper will explore the above challenges in 3D HVM and will present solutions and trade-offs using a systemslevel approach | SET Saint-Jeoire, France |
| Die Attach Bonding using High-frequency Ultrasonic Energy for High-temperature application | June 2014 |
Room-temperature die-attach bonding using ultrasonic energy was evaluated on Cu/In and Cu/Sn-3Ag metal stacks. | IME – Journal of Electronics materials (abstract) |
| Wafer-level 3D integration with 5 micron interconnect pitch for infrared imaging applications | June 2014 |
The use of 3D integration technology in focal plane array imaging devices has been shown to increase imaging capability while simultaneously decreasing device area and power consumption, as compared to analogous 2D designs. | RTI International |
| High Density Interconnect Bonding of Heterogeneous Materials Using Non-Collapsible µbumps at 10 μm Pitch | June 2014 |
Report on a successful demonstration of the use and reliability of CU/SN interconnection of heterogeneous semiconductor die | RTI International |
| Flip-Chip Assembly FPA | ORION 2014 Int’l Conference on Photoelectronics and Night Vision Devices |
Flip-Chip Assembly for Focal Plane Array | SET |
| Chip to wafer cooper direct bonding electrical characterization and thermal cycling | December 2013 |
Study of the recent achievements in cooper direct bonding technology with oxide/cooper mixed surface | CEA – LETI, MINATEC Campus |
| Micro-tube insertion into aluminum pads: Simulation and experimental validations | ECTC 2013 This material is posted here with permission of IEEE. |
Ultra-fine pitch flip | CEA – LETI, MINATEC Campus |
| Aluminum to aluminum Bonding at Room Temperature | ECTC 2013 This material is posted here with permission of IEEE. |
High density and very low pitches face to face aluminum/aluminum cold bonding is feasable when using aluminum coated micro-tubes inserted into aluminum pads | CEA – LETI, MINATEC Campus |
| Die-to-Die and Die-to-Wafer Bonding solution for High Density, Fine Pitch Micro-Bumped Die | Device Packaging 2012 This material is posted here with permission of IMAPS. |
Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a die-to-die and die-to-wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10µm micro-bumps at 20µm pitch. | SET, IMEC |
| High Accuracy Chip-to-Chip or Chip-to-Wafer Bonding methods for 3D-IC integration |
MINAPAD 2012 This material is posted here with permission of IMAPS. |
This paper explores the chip-to-chip and chip-to-wafer alignment schemes and the associated bonding techniques, including insitu reflow or thermo-compression with a local oxide reduction contributing to higher yield with reduction of the force or the temperature requirements. | SET
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| Process and Equipment Enhancements for C2W bonding in a 3D Integration Scheme | IWLPC 2011 Originally published in the IWLPC Proceedings. |
This paper reviews three major areas of process or equipment development, the throughput enhancement by using a sacrificial adhesive to temporarily tack the dice before collective bonding, the in-situ removal and prevention of surface oxides at the bonding interface, and the local environmental control to reduce particulates and other airborne contaminants. | SETNA, Sematech, SET |
| A 10 μm Pitch Interconnection Technology using Micro Tube Insertion into Al-Cu for 3D Applications | ECTC 2011 This material is posted here with permission of IEEE. |
Future 3-D applications require a very low pitch for interstrata vertical interconnection. The last ITRS assessment for vertical interconnection predicts a need for… | CEA-LETI, Minatec, LEM3-CNRS |
| Low Profile 3D Silicon-on-Silicon Multi-chip Assembly | ECTC 2011 This material is posted here with permission of IEEE. |
The focus of this paper is multi-chip 3D silicon-on-silicon assembly using low-profile lead-free (Sn-Cu) solder interconnects. | IBM T.J. Watson Research Center |
| Low Temperature Bonding of High Density Large Area Array Interconnects for 3D Integration | IMAPS 2011 This material is posted here with permission of IMAPS |
The results of bonding and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermo-compression bonded dice…. | RTI International |
| Chip-to-Wafer Technologies for High Density 3D Integration | MINAPAD 2011 This material is posted here with permission of IMAPS |
CEA-Leti partnering with SET, STMicroelectronics, ALES and CNRS-CEMES on advanced Chip-to-Wafer technologies for 3D Integration in the frame of the PROCEED project, a 4.2 Million Euros, 24 months project supported by French FIU (Fond Interministeriel Unique). Started in 2009, the goal of the PROCEED project is to demonstrate high alignment accuracy (<1µm) of chip-to-wafer structures made by direct metallic bonding. | CEA Leti, Minatec campus, CNRS Cemes, ALES, SET, ST Microelectronics |
| 3D-IC Integration using D2C or D2W Alignment Schemes together with Local Oxide Reduction | Device Packaging 2011 This material is posted here with permission of IMAPS |
3-Dimensional interconnection of high density integrated circuits enables building devices with greater functionality with higher performances in a smaller space. This paper explores the chip-to-chip and chip-to-wafer alignment and the associated bonding techniques such as in-situ reflow or thermocompression with a local oxide reduction which contributes to higher yield together with reduction of the force or temperature requirements. | SET, SETNA
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| Embedded active device packaging technology for real DDR2 memory chips | IWLPC 2010 Originally published in the IWLPC Proceedings |
As high-speed, high-density, and high-performance are the primary IC development targets, packaging becomes key technology… | Industrial Technology Research Institute (ITRI) |
| Flip-chip die bonding: an enabling technology for 3D integration | IWLPC 2010 Originally published in the IWLPC Proceedings |
3-Dimensional Integration of Integrated Circuits is a method to build greater functionality into ever-smaller spaces for electronic circuitry, wherein dice of varying sizes, materials, or even application types are electrically and mechanically bonded together | SET NA, SET |
| Fabrication and performance of InAs/GaSb-based superlattice LWIR detectors | SPIE Defense, Sensing & Security June 2010Copyright 2010 SPIE |
InAs/GaSb-based type II superlattices (T2SL) offer a manufacturable FPA technology with FPA size, scalability and cost advantages over HgCdTe. | HRL Laboratories |
| Ultrathin 3D ACA FlipChip-In-Flex Technology | ECTC June 2010This material is posted here with permission of IEEE. |
Die thickness of common, high-volume chip stacks range between 50-100 µm while thinning industry aims towards ultrathin… | Berlin Technical University, NB Technologies and Fraunhofer IZM. |
| Three Chips Stacking with Low Volume Solder Using Single Re-Flow Process | ECTC June 2010This material is posted here with permission of IEEE. |
Miniaturized 3D package with shorter distances between chips are needed for the mobile and high frequency applications. | Institute of Microelectronics – A*STAR |
| Insertion Bonding: A Novel Cu-Cu Bonding Approach for 3D Integration |
ECTC 2010 This material is posted here with permission of IEEE. |
A novel low temperature Cu-Cu bonding approach called the insertion bonding technique has been developed. | IMEC and the Katholieke Universiteit Leuven |
| Die-to-wafer bonding of thin dies using a 2-step approach: high accuracy placement, then gang bonding |
Device Packaging 2010 This material is posted here with permission of IMAPS. |
25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 108 µm and 408 µm… | SET, IMEC |
 Technical Bulletin N°3 |
February 2010 | The SET Technical Bulletin is a compilation of technical articles written by our clients. Each article provides unique insights into the exciting area of C2W and C2C bonding. | CEA-Leti, IMEC, ITRI,IME-A*Star, RTI, etc… |
| RF MEMS and flip-chip for space flight demonstrator |
June 2009 | The next generation of telecommunication satellites payloads will require higher performances and higher.. | Thales Alenia Space |
| Electrical characterization of high count, 10 µm pitch, room-temperature vertical interconnections | Device Packaging 2009 This material is posted here with permission of IMAPS. |
In order to increase the format of heterogeneous staring arrays to 2Kx2K pixels or even larger complexities, limited substrate size and cost. | CEA-LETI |
| Reflow soldering and Tip in Buried Box (TB2) Techniques for Ultrafine Pitch Megapixels Imaging Array | ECTC 2008 This material is posted here with permission of IEEE. |
Flip chip is a high-density and highly reliable interconnection technology which is mandatory for the fabrication of high end heterogeneous imaging arrays. The control of ultra-fine pitch (10µm) and high bumps count flip-chip bonding technology represents a challenge on the roadmap of next generation devices. This paper describes and compares in details two new flip chip technologies that can address the challenges at the 10µm pitch node: a modified reflow soldering technology and a thermocompression “tip in buried box” (TB2) insertion technology. |
CEA-LETI |